The present invention relates in general to field effect transistors, and in particular to trench metal-oxide semiconductor field-effect transistors ("MOSFETs"), and methods of their manufacture.
FIG. 1 is a simplified cross section of a portion of a typical trench MOSFET. A trench 10 is lined with an electrically insulating material 12 and filled with a conductive material 14, which forms the gate. The trench, and hence the gate, extend into a drain region 16 (in this case an n-type region for an n-channel device), which may be electrically contacted through the substrate of the device. A source region 18 opposite the drain region forms an active region 20 adjacent the gate, between the source and drain.
The gate conductive material may be doped polysilicon or the like, and forms an overlap 22 with the drain and another overlap 24 with the source. The overlaps ensure that the active region turns on when voltage is applied to the gate. In conventional devices, the overlap is achieved by implanting a mobile dopant, such as phosphorous, in the source region, and then driving the dopant into the substrate such that it overlaps the gate. The dopant diffuses laterally as well as vertically, thus consuming space between gates of adjacent cells.
Trench transistors are often used in power-handling applications, such as DC-DC conversion, power switching, as in a computer power management circuitry, for example. Trench transistors often operate at 5-100 V, as compared to 2-5 V for a logic-type MOSFET. The gate of a trench transistor is made relatively "wide" to improve the current-handling capability of the trench transistor, and a heavy body 30 is formed to make the device more rugged and able to operate more effectively during switching.
Heavy body 30 is a relatively highly doped region of the same conductivity type as well 32 of the device. Heavy body 30 suppresses the parasitic bipolar transistor turn on between the collector and well region 32, which would result in an uncontrolled current flow (i.e. not controlled by the gate of the device), typically leading to cell or device failure. In a double-diffused (DMOS) trench FET, the effectiveness of the heavy body may be compromised if the source dopant (e.g., Phosphorus) compensates the heavy body dopant (e.g., Boron) resulting in lightly doped interface regions .
The section of the trench transistor shown in FIG. 1 is often referred to as a "cell", because it contains one portion of the gate that is typically repeated across the die. Trench transistor cells are typically laid-out in either a "grid" pattern, as shown in FIG. 2, forming a "closed cell" configuration, or a "stripe" pattern, as shown in FIG. 3, forming an "open cell" configuration. In either arrangement, the several cells of a single trench transistor are typically biased with a nominal V.sub.GS and a nominal V.sub.DS that are applied to each cell according to known methods.
Typically, the trench is filled with conductive material by conformally depositing the conductive material over the substrate, and then etching the conductive material off the surface of the substrate and into the trenches, leaving the conductive material in the trenches to form a gate structure. The conductive material is "overetched", that is, etched to a greater degree to completely remove any residue of the conductive material across the surface of the entire substrate. The degree of overetching is difficult to control accurately and can vary according to a number of parameters, such as the nominal thickness of the conductive material and the uniformity of the etch rate across the substrate. Referring again to FIG. 1, the depth of the top of gate 26 from the surface of substrate 28 can vary, as can the overlap 24 between the gate and the source.
Thus, it is desirable to provide a method that will produce a trench transistor with a large and effective heavy body and wherein the gate will reliably overlap the source region. It is further desirable to form the gate-source overlap in a controlled manner to result in devices with more consistent and superior performance characteristics.